Factorial program in verilog using task

To avoid this problem a keyword automatic is added to make the task reentrant. Function can be used if there is no requirement for specifying delays, timing control constructs or events. There is at least one input argument is needed to use function.

Function will return a single value and it usually uses for calculations. Also note that it cannot have output or inout arguments. As it cannot handle timing control statement, delays etc and executes in 0 simulation time, it can only enable another function and not task. Below example shows how to calculate parity using function. A simple code, but always used in the designs. If normal functions are called recursively, the results are non-deterministic because both calls operate on the same variable space.

But by using automatic keyword, all function declarations are allocated dynamically for each call and operate on independent variable space. Following is a well known example for automatic function. Constant function can be used to instead of constants. If signed operation needs to performed on return value, then that function must be defined using signed keyword.

This is the right answer. Thanks for pointing out. Thanks in advance. This depends on how you invoke the tasks in your code. You can model it as per your requirement. When we write functions in verilog, we can declare and use local variables. This means that we can declare variables in the function which can't be accessed outside of the function it is declared in.

For example, if we declare a function within a module block then all of the variables declared in that module can be accessed and modified by the function. For this example, we will write a function which takes 2 input arguments and returns the sum of them. We use verilog integer types for the input arguments and the return types. We must also make use of the verilog addition operator in order to calculate the sum of the inputs. As we have previously discussed, there are two methods we can use to declare verilog functions and both of these are shown in the code below.

We can also simulate this example using EDA playground. When we want to use a function in another part of our verilog design, we have to call it. The method we use to do this is similar to other programming languages. When we call a function we pass parameters to the function in the same order as we declared them.

This is known as positional association and it means that the order we declare our arguments in is very important. The code snippet below shows how we would use positional association to call the addition example function. We can also use the verilog automatic keyword to declare a function as reentrant.

However, the automatic keyword was introduced in the verilog standard meaning that we can't write reentrant functions when working with the verilog standard. When we declare a function as reentrant, the variables and arguments within the function are dynamically allocated.

In contrast, normal functions use static allocation for internal variables and arguments. When we we write a normal function, all of the memory which is used to perform the processing of the function is allocated only once. This is process is known as static memory allocation in computer science. As a result of this, our simulation software must execute the function in it's entirety before it can use the function again. This also means that the memory the function uses is never deallocated.

As a result of this, any values stored in this memory will maintain their value between calls to the function. In contrast, functions which use the automatic keyword allocate memory whenever the function is called. The memory is then deallocated once the function has finished with it. As a result of this, our simulation software can execute multiple instances of an automatic function.

We can use the automatic keyword to write recursive functions in verilog. This means we can create functions which call themselves to perform a calculation. As an example, one common use case for recursive functions is calculating the factorial of a given number. The code snippet below shows how we would use the automatic keyword to write a recursive function in verilog. Just like functions, we use tasks to implement small sections of code which we can reuse throughout our design.

In verilog, a task can have any number of inputs and can also generate any number of outputs. This is in contrast to functions which can only return a single value. Unlike functions, we can also use time consuming constructs such as wait, posedge or delays within a task.

As a result of this, we can use both blocking and non-blocking assignment in verilog tasks. These features mean tasks are best used to implement simple pieces of code which are repeated several times in our design. We write the code for tasks in the verilog module which will be used to call the task. We can also create global tasks which are shared by all modules in a given file.

To do this we simply write the code for the task outside of the module declarations in the file. As with functions, there are two ways in which we can declare a task but the performance of both approaches is the same. When we write tasks which declare the inputs and outputs within the task body, we must use the begin and end keywords as well. However, when we use inline declaration for the inputs and outputs, we can omit the begin and end keywords.

When we write tasks in verilog, we can declare and use local variables. This means that we can create variables in the task which can't be accessed outside of the task it is declared in. Yes, functions are synthesizable! Often functions are created in the file they are used in. The example below demonstrates this. Automatic is a term borrowed from C which allows the function to be re-entrant.

A re-entrant function is one in which the items declared within the function are allocated upon every individual call of the function, as opposed to being shared between all calls of the function.

This could be a problem in a simulation environment if code is forked and calls the same function at the same time. Race conditions can develop. In C, all variables are automatic by default. In order to make them not automatic, they must be declared as static.